In my previous MLIR compiler project, I built a small tensor compiler using the MLIR framework. While working on it, I realized how much complexity the framework handles for me, from lowering operations through existing compiler infrastructure to generating executable code. This made me curious about what happens underneath these abstractions, particularly when compiling for custom hardware rather than a conventional CPU. For this project, I want to explore two things: how AI

A look at the initial FPGA architecture for my accelerator-compiler co-design project, covering the custom scalar compute unit, instruction execution, memory-mapped I/O, hardware verification, and lessons learned from building and testing the system on a Terasic DE10-Lite.